15 lines
369 B
VHDL
15 lines
369 B
VHDL
-- generated by newgenasym Thu Jun 04 18:01:30 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \100el05\ is
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port (
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IN1: IN STD_LOGIC;
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\in1*\: IN STD_LOGIC;
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IN2: IN STD_LOGIC;
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\in2*\: IN STD_LOGIC;
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\out\: OUT STD_LOGIC;
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\out*\: OUT STD_LOGIC);
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end \100el05\;
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