40 lines
669 B
Verilog
40 lines
669 B
Verilog
// generated by newgenasym Sun Mar 01 22:00:55 2015
|
|
|
|
|
|
module mc10e016 (\ce* , clk, gnd0, gnd1, gnd2, gnd3, mr, p0, p1, p2, p3, p4, p5, p6,
|
|
p7, \pe* , q0, q1, q2, q3, q4, q5, q6, q7, \tc* , tcld, vee);
|
|
input \ce* ;
|
|
input clk;
|
|
input gnd0;
|
|
input gnd1;
|
|
input gnd2;
|
|
input gnd3;
|
|
input mr;
|
|
input p0;
|
|
input p1;
|
|
input p2;
|
|
input p3;
|
|
input p4;
|
|
input p5;
|
|
input p6;
|
|
input p7;
|
|
input \pe* ;
|
|
output q0;
|
|
output q1;
|
|
output q2;
|
|
output q3;
|
|
output q4;
|
|
output q5;
|
|
output q6;
|
|
output q7;
|
|
output \tc* ;
|
|
input tcld;
|
|
input vee;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|