36 lines
1.1 KiB
VHDL
36 lines
1.1 KiB
VHDL
-- generated by newgenasym Sun Mar 01 22:00:55 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mc10e016 is
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port (
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\ce*\: IN STD_LOGIC;
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CLK: IN STD_LOGIC;
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GND0: IN STD_LOGIC;
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GND1: IN STD_LOGIC;
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GND2: IN STD_LOGIC;
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GND3: IN STD_LOGIC;
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MR: IN STD_LOGIC;
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P0: IN STD_LOGIC;
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P1: IN STD_LOGIC;
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P2: IN STD_LOGIC;
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P3: IN STD_LOGIC;
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P4: IN STD_LOGIC;
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P5: IN STD_LOGIC;
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P6: IN STD_LOGIC;
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P7: IN STD_LOGIC;
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\pe*\: IN STD_LOGIC;
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Q0: OUT STD_LOGIC;
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Q1: OUT STD_LOGIC;
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Q2: OUT STD_LOGIC;
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Q3: OUT STD_LOGIC;
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Q4: OUT STD_LOGIC;
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Q5: OUT STD_LOGIC;
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Q6: OUT STD_LOGIC;
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Q7: OUT STD_LOGIC;
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\tc*\: OUT STD_LOGIC;
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TCLD: IN STD_LOGIC;
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VEE: IN STD_LOGIC);
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end mc10e016;
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