37 lines
1.1 KiB
VHDL
37 lines
1.1 KiB
VHDL
-- generated by newgenasym Sun Mar 01 00:00:53 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mc10e101 is
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port (
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D0A: IN STD_LOGIC;
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D0B: IN STD_LOGIC;
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D0C: IN STD_LOGIC;
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D0D: IN STD_LOGIC;
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D1A: IN STD_LOGIC;
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D1B: IN STD_LOGIC;
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D1C: IN STD_LOGIC;
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D1D: IN STD_LOGIC;
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D2A: IN STD_LOGIC;
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D2B: IN STD_LOGIC;
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D2C: IN STD_LOGIC;
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D2D: IN STD_LOGIC;
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D3A: IN STD_LOGIC;
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D3B: IN STD_LOGIC;
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D3C: IN STD_LOGIC;
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D3D: IN STD_LOGIC;
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GND0: IN STD_LOGIC;
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GND1: IN STD_LOGIC;
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GND2: IN STD_LOGIC;
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Q0: OUT STD_LOGIC;
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\q0*\: OUT STD_LOGIC;
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Q1: OUT STD_LOGIC;
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\q1*\: OUT STD_LOGIC;
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Q2: OUT STD_LOGIC;
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\q2*\: OUT STD_LOGIC;
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Q3: OUT STD_LOGIC;
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\q3*\: OUT STD_LOGIC;
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VEE: IN STD_LOGIC);
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end mc10e101;
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