37 lines
1.1 KiB
VHDL
37 lines
1.1 KiB
VHDL
-- generated by newgenasym Sat Feb 28 18:17:35 2015
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity mc10e116 is
|
|
port (
|
|
D0: IN STD_LOGIC;
|
|
\d0*\: IN STD_LOGIC;
|
|
D1: IN STD_LOGIC;
|
|
\d1*\: IN STD_LOGIC;
|
|
D2: IN STD_LOGIC;
|
|
\d2*\: IN STD_LOGIC;
|
|
D3: IN STD_LOGIC;
|
|
\d3*\: IN STD_LOGIC;
|
|
D4: IN STD_LOGIC;
|
|
\d4*\: IN STD_LOGIC;
|
|
GND0: IN STD_LOGIC;
|
|
GND1: IN STD_LOGIC;
|
|
GND2: IN STD_LOGIC;
|
|
GND3: IN STD_LOGIC;
|
|
GND4: IN STD_LOGIC;
|
|
GND5: IN STD_LOGIC;
|
|
Q0: OUT STD_LOGIC;
|
|
\q0*\: OUT STD_LOGIC;
|
|
Q1: OUT STD_LOGIC;
|
|
\q1*\: OUT STD_LOGIC;
|
|
Q2: OUT STD_LOGIC;
|
|
\q2*\: OUT STD_LOGIC;
|
|
Q3: OUT STD_LOGIC;
|
|
\q3*\: OUT STD_LOGIC;
|
|
Q4: OUT STD_LOGIC;
|
|
\q4*\: OUT STD_LOGIC;
|
|
VBB: OUT STD_LOGIC;
|
|
VEE: IN STD_LOGIC);
|
|
end mc10e116;
|