Tubii_Tk2/Parts/parts/ecl/mc10h104/entity/verilog.v
2015-02-28 18:43:30 -05:00

29 lines
441 B
Verilog

// generated by newgenasym Sat Feb 28 17:31:57 2015
module mc10h104 (a1, a2, a3, a4, b1, b2, b3, b4, gnd1, gnd2, q1, q2, q3, q4, \q4* ,
vee);
input a1;
input a2;
input a3;
input a4;
input b1;
input b2;
input b3;
input b4;
input gnd1;
input gnd2;
output q1;
output q2;
output q3;
output q4;
output \q4* ;
input vee;
initial
begin
end
endmodule