25 lines
707 B
VHDL
25 lines
707 B
VHDL
-- generated by newgenasym Sat Feb 28 17:31:57 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mc10h104 is
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port (
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A1: IN STD_LOGIC;
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A2: IN STD_LOGIC;
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A3: IN STD_LOGIC;
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A4: IN STD_LOGIC;
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B1: IN STD_LOGIC;
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B2: IN STD_LOGIC;
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B3: IN STD_LOGIC;
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B4: IN STD_LOGIC;
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GND1: IN STD_LOGIC;
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GND2: IN STD_LOGIC;
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Q1: OUT STD_LOGIC;
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Q2: OUT STD_LOGIC;
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Q3: OUT STD_LOGIC;
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Q4: OUT STD_LOGIC;
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\q4*\: OUT STD_LOGIC;
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VEE: IN STD_LOGIC);
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end mc10h104;
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