25 lines
707 B
VHDL
25 lines
707 B
VHDL
-- generated by newgenasym Sat Mar 07 23:06:20 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mc10h116 is
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port (
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D1: IN STD_LOGIC;
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\d1*\: IN STD_LOGIC;
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D2: IN STD_LOGIC;
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\d2*\: IN STD_LOGIC;
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D3: IN STD_LOGIC;
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\d3*\: IN STD_LOGIC;
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GND1: IN STD_LOGIC;
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GND2: IN STD_LOGIC;
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Q1: OUT STD_LOGIC;
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\q1*\: OUT STD_LOGIC;
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Q2: OUT STD_LOGIC;
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\q2*\: OUT STD_LOGIC;
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Q3: OUT STD_LOGIC;
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\q3*\: OUT STD_LOGIC;
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VBB: OUT STD_LOGIC;
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VEE: IN STD_LOGIC);
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end mc10h116;
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