25 lines
707 B
VHDL
25 lines
707 B
VHDL
-- generated by newgenasym Sat Feb 28 18:41:09 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mc10h124 is
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port (
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A_IN: IN STD_LOGIC;
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A_OUT: OUT STD_LOGIC;
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\a_out*\: OUT STD_LOGIC;
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B_IN: IN STD_LOGIC;
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B_OUT: OUT STD_LOGIC;
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\b_out*\: OUT STD_LOGIC;
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C_IN: IN STD_LOGIC;
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C_OUT: OUT STD_LOGIC;
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\c_out*\: OUT STD_LOGIC;
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COMMON: IN STD_LOGIC;
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D_IN: IN STD_LOGIC;
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D_OUT: OUT STD_LOGIC;
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\d_out*\: OUT STD_LOGIC;
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GND: IN STD_LOGIC;
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VCC: IN STD_LOGIC;
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VEE: IN STD_LOGIC);
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end mc10h124;
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