29 lines
462 B
Verilog
29 lines
462 B
Verilog
// generated by newgenasym Sat Feb 28 23:31:48 2015
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module mc10h131 (cc, \ce1* , \ce2* , d1, d2, gnd1, gnd2, q1, \q1* , q2, \q2* , r1, r2, s1,
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s2, vee);
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input cc;
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input \ce1* ;
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input \ce2* ;
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input d1;
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input d2;
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input gnd1;
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input gnd2;
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output q1;
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output \q1* ;
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output q2;
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output \q2* ;
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input r1;
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input r2;
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input s1;
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input s2;
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input vee;
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initial
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begin
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end
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endmodule
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