25 lines
707 B
VHDL
25 lines
707 B
VHDL
-- generated by newgenasym Sat Feb 28 23:31:48 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mc10h131 is
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port (
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CC: IN STD_LOGIC;
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\ce1*\: IN STD_LOGIC;
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\ce2*\: IN STD_LOGIC;
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D1: IN STD_LOGIC;
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D2: IN STD_LOGIC;
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GND1: IN STD_LOGIC;
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GND2: IN STD_LOGIC;
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Q1: OUT STD_LOGIC;
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\q1*\: OUT STD_LOGIC;
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Q2: OUT STD_LOGIC;
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\q2*\: OUT STD_LOGIC;
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R1: IN STD_LOGIC;
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R2: IN STD_LOGIC;
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S1: IN STD_LOGIC;
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S2: IN STD_LOGIC;
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VEE: IN STD_LOGIC);
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end mc10h131;
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