33 lines
588 B
Verilog
33 lines
588 B
Verilog
// generated by newgenasym Sun Mar 01 15:35:05 2015
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module sy100el91l (d0, \d0* , d1, \d1* , d2, \d2* , gnd0, gnd1, pecl_vbb0, pecl_vbb1,
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q0, \q0* , q1, \q1* , q2, \q2* , vcc0, vcc1, vcc2, vee);
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input d0;
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input \d0* ;
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input d1;
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input \d1* ;
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input d2;
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input \d2* ;
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input gnd0;
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input gnd1;
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output pecl_vbb0;
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output pecl_vbb1;
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output q0;
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output \q0* ;
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output q1;
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output \q1* ;
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output q2;
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output \q2* ;
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input vcc0;
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input vcc1;
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input vcc2;
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input vee;
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initial
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begin
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end
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endmodule
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