27 lines
421 B
Verilog
27 lines
421 B
Verilog
// generated by newgenasym Sat Feb 28 13:09:10 2015
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module \74f164 (cp, dsa, dsb, gnd, \mr* , q, q0, q1, q2, q3, q4, q5, q6, q7, vcc);
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input cp;
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input dsa;
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input dsb;
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input gnd;
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input \mr* ;
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output [7:0] q;
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output q0;
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output q1;
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output q2;
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output q3;
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output q4;
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output q5;
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output q6;
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output q7;
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input vcc;
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initial
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begin
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end
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endmodule
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