25 lines
705 B
VHDL
25 lines
705 B
VHDL
-- generated by newgenasym Sat Feb 28 21:51:39 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ad96687 is
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port (
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GND1: IN STD_LOGIC;
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GND2: IN STD_LOGIC;
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IN_N1: INOUT STD_LOGIC;
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IN_N2: INOUT STD_LOGIC;
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IN_P1: INOUT STD_LOGIC;
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IN_P2: INOUT STD_LOGIC;
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LE1: IN STD_LOGIC;
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\le1*\: IN STD_LOGIC;
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LE2: IN STD_LOGIC;
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\le2*\: IN STD_LOGIC;
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Q1: OUT STD_LOGIC;
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\q1*\: OUT STD_LOGIC;
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Q2: OUT STD_LOGIC;
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\q2*\: OUT STD_LOGIC;
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\vs+\: IN STD_LOGIC;
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\vs-\: IN STD_LOGIC);
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end ad96687;
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