Tubii_Tk2/Parts/parts/misc/conn14/entity/verilog.v
2015-05-26 21:42:23 -04:00

26 lines
412 B
Verilog

// generated by newgenasym Tue May 26 20:36:35 2015
module conn14 (\1 , \10 , \11 , \12 , \13 , \14 , \2 , \3 , \4 , \5 , \6 , \7 , \8 , \9 );
inout \1 ;
inout \10 ;
inout \11 ;
inout \12 ;
inout \13 ;
inout \14 ;
inout \2 ;
inout \3 ;
inout \4 ;
inout \5 ;
inout \6 ;
inout \7 ;
inout \8 ;
inout \9 ;
initial
begin
end
endmodule