17 lines
437 B
VHDL
17 lines
437 B
VHDL
-- generated by newgenasym Mon Mar 02 15:48:32 2015
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity ds90lv027 is
|
|
port (
|
|
D1: IN STD_LOGIC;
|
|
D2: IN STD_LOGIC;
|
|
GND: IN STD_LOGIC;
|
|
Q1: OUT STD_LOGIC;
|
|
\q1*\: OUT STD_LOGIC;
|
|
Q2: OUT STD_LOGIC;
|
|
\q2*\: OUT STD_LOGIC;
|
|
VCC: IN STD_LOGIC);
|
|
end ds90lv027;
|