17 lines
230 B
Verilog
17 lines
230 B
Verilog
// generated by newgenasym Wed Mar 18 18:31:10 2015
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module foxclock (ed, gnd, out, \out* , vdd);
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input ed;
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input gnd;
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output out;
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output \out* ;
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input vdd;
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initial
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begin
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end
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endmodule
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