14 lines
333 B
VHDL
14 lines
333 B
VHDL
-- generated by newgenasym Wed Mar 18 18:31:10 2015
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity foxclock is
|
|
port (
|
|
ED: IN STD_LOGIC;
|
|
GND: IN STD_LOGIC;
|
|
\out\: OUT STD_LOGIC;
|
|
\out*\: OUT STD_LOGIC;
|
|
VDD: IN STD_LOGIC);
|
|
end foxclock;
|