25 lines
709 B
VHDL
25 lines
709 B
VHDL
-- generated by newgenasym Sat Mar 07 22:28:59 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity hct123 is
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port (
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CEXT1: INOUT STD_LOGIC;
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CEXT2: INOUT STD_LOGIC;
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GND: IN STD_LOGIC;
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\in_a1*\: IN STD_LOGIC;
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\in_a2*\: IN STD_LOGIC;
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IN_B1: IN STD_LOGIC;
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IN_B2: IN STD_LOGIC;
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Q1: OUT STD_LOGIC;
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\q1*\: OUT STD_LOGIC;
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Q2: OUT STD_LOGIC;
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\q2*\: OUT STD_LOGIC;
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\rd1*\: IN STD_LOGIC;
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\rd2*\: IN STD_LOGIC;
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\rext/cext1\: INOUT STD_LOGIC;
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\rext/cext2\: INOUT STD_LOGIC;
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VCC: IN STD_LOGIC);
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end hct123;
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