24 lines
677 B
VHDL
24 lines
677 B
VHDL
-- generated by newgenasym Sun Mar 01 15:00:23 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity sy100el34l is
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port (
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CLK: IN STD_LOGIC;
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\clk*\: IN STD_LOGIC;
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\en*\: IN STD_LOGIC;
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GND0: IN STD_LOGIC;
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GND1: IN STD_LOGIC;
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GND2: IN STD_LOGIC;
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MR: IN STD_LOGIC;
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Q0: OUT STD_LOGIC;
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\q0*\: OUT STD_LOGIC;
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Q1: OUT STD_LOGIC;
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\q1*\: OUT STD_LOGIC;
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Q2: OUT STD_LOGIC;
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\q2*\: OUT STD_LOGIC;
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VBB: OUT STD_LOGIC;
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VEE: IN STD_LOGIC);
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end sy100el34l;
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