Tubii_Tk2/Parts/parts/regulators/lm1117/entity/verilog.v
2015-05-19 16:37:11 -04:00

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Verilog

// generated by newgenasym Tue May 19 16:36:07 2015
module lm1117 (ground, \input , \output , output_2);
inout ground;
input \input ;
output \output ;
output output_2;
initial
begin
end
endmodule