15 lines
363 B
VHDL
15 lines
363 B
VHDL
-- generated by newgenasym Thu May 28 12:21:41 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity lm2596 is
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port (
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FB: INOUT STD_LOGIC;
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GND: IN STD_LOGIC;
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\on*\: IN STD_LOGIC;
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TAB: INOUT STD_LOGIC;
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VIN: INOUT STD_LOGIC;
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VOUT: INOUT STD_LOGIC);
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end lm2596;
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