23 lines
637 B
VHDL
23 lines
637 B
VHDL
-- generated by newgenasym Sun Mar 01 02:51:03 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \74f06\ is
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port (
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D1: IN STD_LOGIC;
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D2: IN STD_LOGIC;
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D3: IN STD_LOGIC;
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D4: IN STD_LOGIC;
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D5: IN STD_LOGIC;
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D6: IN STD_LOGIC;
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GND: IN STD_LOGIC;
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\q1*\: OUT STD_LOGIC;
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\q2*\: OUT STD_LOGIC;
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\q3*\: OUT STD_LOGIC;
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\q4*\: OUT STD_LOGIC;
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\q5*\: OUT STD_LOGIC;
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\q6*\: OUT STD_LOGIC;
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VCC: IN STD_LOGIC);
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end \74f06\;
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