25 lines
711 B
VHDL
25 lines
711 B
VHDL
-- generated by newgenasym Sat Feb 28 13:30:58 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity \74hct165\ is
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port (
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\ce*\: IN STD_LOGIC;
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CP: IN STD_LOGIC;
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D0: IN STD_LOGIC;
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D1: IN STD_LOGIC;
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D2: IN STD_LOGIC;
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D3: IN STD_LOGIC;
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D4: IN STD_LOGIC;
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D5: IN STD_LOGIC;
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D6: IN STD_LOGIC;
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D7: IN STD_LOGIC;
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DS: IN STD_LOGIC;
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GND: IN STD_LOGIC;
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\pl*\: IN STD_LOGIC;
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Q7: OUT STD_LOGIC;
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\q7*\: OUT STD_LOGIC;
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VCC: IN STD_LOGIC);
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end \74hct165\;
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