33 lines
512 B
Verilog
33 lines
512 B
Verilog
// generated by newgenasym Sun Mar 01 21:01:18 2015
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module \74hct273 (cp, d0, d1, d2, d3, d4, d5, d6, d7, gnd, \mr* , q0, q1, q2, q3, q4, q5,
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q6, q7, vcc);
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input cp;
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input d0;
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input d1;
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input d2;
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input d3;
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input d4;
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input d5;
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input d6;
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input d7;
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input gnd;
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input \mr* ;
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output q0;
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output q1;
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output q2;
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output q3;
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output q4;
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output q5;
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output q6;
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output q7;
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input vcc;
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initial
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begin
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end
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endmodule
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