26 lines
387 B
Verilog
26 lines
387 B
Verilog
// generated by newgenasym Sat May 23 15:11:16 2015
|
|
|
|
|
|
module \74lv07a (a1, a2, a3, a4, a5, a6, gnd, vcc, y1, y2, y3, y4, y5, y6);
|
|
input a1;
|
|
input a2;
|
|
input a3;
|
|
input a4;
|
|
input a5;
|
|
input a6;
|
|
input gnd;
|
|
input vcc;
|
|
output y1;
|
|
output y2;
|
|
output y3;
|
|
output y4;
|
|
output y5;
|
|
output y6;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|