25 lines
707 B
VHDL
25 lines
707 B
VHDL
-- generated by newgenasym Mon Jun 01 12:06:56 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ds102350 is
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port (
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\clk/p1\: IN STD_LOGIC;
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\d/p2\: IN STD_LOGIC;
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GND: IN STD_LOGIC;
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\in\: IN STD_LOGIC;
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\le*\: IN STD_LOGIC;
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MS: IN STD_LOGIC;
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\out\: OUT STD_LOGIC;
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P3: IN STD_LOGIC;
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P4: IN STD_LOGIC;
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P5: IN STD_LOGIC;
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P6: IN STD_LOGIC;
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P7: IN STD_LOGIC;
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PS: IN STD_LOGIC;
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PWM: OUT STD_LOGIC;
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\q/p0\: IN STD_LOGIC;
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VCC: IN STD_LOGIC);
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end ds102350;
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