Tubii_Tk2/Parts/parts/ttl/sn74s32/entity/verilog.v

26 lines
383 B
Verilog

// generated by newgenasym Tue Apr 21 13:20:23 2015
module sn74s32 (a1, a2, a3, a4, b1, b2, b3, b4, gnd, vcc, y1, y2, y3, y4);
input a1;
input a2;
input a3;
input a4;
input b1;
input b2;
input b3;
input b4;
input gnd;
input vcc;
output y1;
output y2;
output y3;
output y4;
initial
begin
end
endmodule