23 lines
637 B
VHDL
23 lines
637 B
VHDL
-- generated by newgenasym Tue Apr 21 13:20:23 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity sn74s32 is
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port (
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A1: IN STD_LOGIC;
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A2: IN STD_LOGIC;
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A3: IN STD_LOGIC;
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A4: IN STD_LOGIC;
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B1: IN STD_LOGIC;
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B2: IN STD_LOGIC;
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B3: IN STD_LOGIC;
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B4: IN STD_LOGIC;
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GND: IN STD_LOGIC;
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VCC: IN STD_LOGIC;
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Y1: OUT STD_LOGIC;
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Y2: OUT STD_LOGIC;
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Y3: OUT STD_LOGIC;
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Y4: OUT STD_LOGIC);
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end sn74s32;
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