20 lines
297 B
Verilog
20 lines
297 B
Verilog
// generated by newgenasym Sun Mar 01 21:37:54 2015
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module sy100el05 (d_a, \d_a* , d_b, \d_b* , gnd, q, \q* , vee);
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input d_a;
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input \d_a* ;
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input d_b;
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input \d_b* ;
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input gnd;
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output q;
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output \q* ;
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input vee;
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initial
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begin
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end
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endmodule
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