17 lines
437 B
VHDL
17 lines
437 B
VHDL
-- generated by newgenasym Sun Mar 01 21:37:54 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity sy100el05 is
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port (
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D_A: IN STD_LOGIC;
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\d_a*\: IN STD_LOGIC;
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D_B: IN STD_LOGIC;
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\d_b*\: IN STD_LOGIC;
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GND: IN STD_LOGIC;
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Q: OUT STD_LOGIC;
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\q*\: OUT STD_LOGIC;
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VEE: IN STD_LOGIC);
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end sy100el05;
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