AllSpiceMirrors/Tubii_Tk2
7
Fork 0
Files Issues Design Reviews Releases Activity
master
Tubii_Tk2/cdssetup/propflow.txt
Eric M 2e97a1c5af Made some rooms and layed them out
2015-03-07 23:39:19 -05:00

254 lines
6.3 KiB
Plaintext
Raw Permalink Blame History

PROPERTY_NAME!OWNER!CONCEPT!ALLEGRO!TRANSFER!WINNING_VALUE!TYPE!
ALT_SYMBOLS!1!1!1!0!0!0!
AUTO_GENERATED_TERM!1!1!1!0!0!0!
AUTO_RENAME!1!1!1!0!0!0!
BOM_IGNORE!1!1!1!0!0!0!
COMPONENT_WEIGHT!1!1!1!0!0!0!
CURRENT!1!1!1!0!0!0!
C_TEMPERATURE!1!1!1!0!0!0!
DENSE_COMPONENT!1!1!1!0!0!0!
DEPTH_STOP!1!1!1!0!0!0!
DEVICE_LABEL!1!1!1!0!0!0!
EMC_COMP_TYPE!1!1!1!0!0!0!
EMC_CRITICAL_IC!1!1!1!0!0!0!
FAILURE_RATE!1!1!1!0!0!0!
FIX_ALL!1!1!1!0!0!0!
FIXED!1!1!1!0!0!0!
HARD_LOCATION!1!1!1!0!0!0!
HEIGHT!1!1!1!0!0!0!
INSERTION_CODE!1!1!1!0!0!0!
J_TEMPERATURE!1!1!1!0!0!0!
MAX_POWER_DISS!1!1!1!0!0!0!
NO_PIN_ESCAPE!1!1!1!0!0!0!
NO_ROUTE!1!1!1!0!0!0!
NO_SWAP_COMP!1!1!1!0!0!0!
NO_SWAP_GATE!1!1!1!0!0!0!
NO_SWAP_GATE_EXT!1!1!1!0!0!0!
NO_SWAP_PIN!1!1!1!0!0!0!
PART_NUMBER!1!1!1!0!0!0!
PIN_ESCAPE!1!1!1!0!0!0!
PLACE_TAG!1!1!1!0!0!0!
RATED_CURRENT!1!1!1!0!0!0!
RATED_MAX_TEMP!1!1!1!0!0!0!
RATED_POWER!1!1!1!0!0!0!
RATED_VOLTAGE!1!1!1!0!0!0!
ROOM!1!1!1!0!0!0!
SIGNAL_MODEL!1!1!1!1!0!0!
TERMINATOR_PACK!1!1!1!0!0!0!
TH_APPLICATION!1!1!1!0!0!0!
TH_CB_RES!1!1!1!0!0!0!
TH_CLEARANCE!1!1!1!0!0!0!
TH_CLEARANCE_AREA!1!1!1!0!0!0!
TH_CLEARANCE_MATERIAL!1!1!1!0!0!0!
TH_COMPLEXITY!1!1!1!0!0!0!
TH_DEV_CLASS!1!1!1!0!0!0!
TH_DEV_TYPE!1!1!1!0!0!0!
TH_FUNC_PARM!1!1!1!0!0!0!
TH_GLUERES!1!1!1!0!0!0!
TH_HEATSINK!1!1!1!0!0!0!
TH_JC_RES!1!1!1!0!0!0!
TH_LOCATION!1!1!1!0!0!0!
TH_PACK_PARM!1!1!1!0!0!0!
TH_QUALITY!1!1!1!0!0!0!
TH_TECHNOLOGY!1!1!1!0!0!0!
TOL!1!1!1!0!0!0!
T_TEMPERATURE!1!1!1!0!0!0!
VALUE!1!1!1!0!0!0!
VOLTAGE!1!1!1!0!0!0!
VOLT_TEMP_MODEL!1!1!1!0!0!0!
HARD_LOCATION!2!1!1!0!0!0!
NO_SWAP_GATE!2!1!1!0!0!0!
NO_SWAP_GATE_EXT!2!1!1!0!0!0!
NO_SWAP_PIN!2!1!1!0!0!0!
REF_DES_FOR_ASSIGN!2!1!1!0!0!0!
SLOTNAME!2!1!1!0!0!0!
SWAP_GROUP!2!1!1!0!0!0!
GROUP!2!1!1!0!0!0!
CLIP_DRAWING!4!1!1!0!0!0!
FIXED!4!1!1!0!0!0!
IDF_OWNER!4!1!1!0!0!0!
MIN_HOLD!4!1!1!0!0!0!
MIN_SETUP!4!1!1!0!0!0!
NET_SHORT!4!1!1!0!0!0!
NO_DRC!4!1!1!0!0!0!
NO_PIN_ESCAPE!4!1!1!0!0!0!
NO_SWAP_PIN!4!1!1!0!0!0!
NO_VIA_CONNECT!4!1!1!0!0!0!
PINUSE!4!1!1!0!0!0!
PIN_ESCAPE!4!1!1!0!0!0!
PIN_SIGNAL_MODEL!4!1!1!1!0!0!
SHORTING_SCHEME!4!1!1!0!0!0!
SUBNET_NAME!4!1!1!0!0!0!
VOLTAGE_SOURCE_PIN!4!1!1!0!0!0!
XTALK_SENSITIVE_TIME!4!1!1!0!0!0!
ASSIGN_TOPOLOGY!3!1!1!0!0!0!
BUS_NAME!3!1!1!0!0!0!
CLK_2OUT_MAX!3!1!1!0!0!0!
CLK_2OUT_MIN!3!1!1!0!0!0!
CLK_SKEW_MAX!3!1!1!0!0!0!
CLK_SKEW_MIN!3!1!1!0!0!0!
CLOCK_NET!3!1!1!0!0!0!
DELAY_RULE!3!1!1!0!0!0!
DIFFERENTIAL_PAIR!3!1!1!0!0!0!
DIFFP_2ND_LENGTH!3!1!1!0!0!0!
DIFFP_LENGTH_TOL!3!1!1!0!0!0!
DRIVER_TERM_VAL!3!1!1!0!0!0!
ECL!3!1!1!0!0!0!
EDGE_SENS!3!1!1!0!0!0!
ELECTRICAL_CONSTRAINT_SET!3!1!1!0!0!0!
EMC_CRITICAL_NET!3!1!1!0!0!0!
FIRST_INCIDENT!3!1!1!0!0!0!
FIXED!3!1!1!0!0!0!
IMPEDANCE_RULE!3!1!1!0!0!0!
LOAD_TERM_VAL!3!1!1!0!0!0!
MATCHED_DELAY!3!1!1!0!0!0!
MAX_BOND_LENGTH!3!1!1!0!0!0!
MAX_BVIA_STAGGER!3!1!1!0!0!0!
MAX_EXPOSED_LENGTH!3!1!1!0!0!0!
MAX_FINAL_SETTLE!3!1!1!0!0!0!
MAX_OVERSHOOT!3!1!1!0!0!0!
MAX_PARALLEL!3!1!1!0!0!0!
MAX_PEAK_XTALK!3!1!1!0!0!0!
MAX_SSN!3!1!1!0!0!0!
MAX_VIA_COUNT!3!1!1!0!0!0!
MAX_XTALK!3!1!1!0!0!0!
MIN_BOND_LENGTH!3!1!1!0!0!0!
MIN_BVIA_GAP!3!1!1!0!0!0!
MIN_BVIA_STAGGER!3!1!1!0!0!0!
MIN_FIRST_SWITCH!3!1!1!0!0!0!
MIN_LINE_WIDTH!3!1!1!0!0!0!
MIN_NECK_WIDTH!3!1!1!0!0!0!
MIN_NOISE_MARGIN!3!1!1!0!0!0!
NET_PHYSICAL_TYPE!3!1!1!0!0!0!
NET_SCHEDULE!3!1!1!0!0!0!
NET_SPACING_TYPE!3!1!1!0!0!0!
NO_GLOSS!3!1!1!0!0!0!
NO_PIN_ESCAPE!3!1!1!0!0!0!
NO_RAT!3!1!1!0!0!0!
NO_RIPUP!3!1!1!0!0!0!
NO_ROUTE!3!1!1!0!0!0!
NO_TEST!3!1!1!0!0!0!
PROBE_NUMBER!3!1!1!0!0!0!
PROPAGATION_DELAY!3!1!1!0!0!0!
PULSE_PARAM!3!1!1!0!0!0!
RATSNEST_SCHEDULE!3!1!1!0!0!0!
RELATIVE_PROPAGATION_DELAY!3!1!1!0!0!0!
ROUTE_PRIORITY!3!1!1!0!0!0!
ROUTE_TO_SHAPE!3!1!1!0!0!0!
SAME_NET!3!1!1!0!0!0!
SHORTING_SCHEME!3!1!1!0!0!0!
SHIELD_NET!3!1!1!0!0!0!
SHIELD_TYPE!3!1!1!0!0!0!
STUB_LENGTH!3!1!1!0!0!0!
SUBNET_NAME!3!1!1!0!0!0!
TESTER_GUARDBAND!3!1!1!0!0!0!
TIMING_DELAY_OVERRIDE!3!1!1!0!0!0!
TOPOLOGY_TEMPLATE!3!1!1!0!0!0!
TOPOLOGY_TEMPLATE_REVISION!3!1!1!0!0!0!
TS_ALLOWED!3!1!1!0!0!0!
VIA_LIST!3!1!1!0!0!0!
VOLTAGE!3!1!1!0!0!0!
VOLTAGE_LAYER!3!1!1!0!0!0!
WEIGHT!3!1!1!0!0!0!
XTALK_ACTIVE_TIME!3!1!1!0!0!0!
XTALK_IGNORE_NETS!3!1!1!0!0!0!
XTALK_SENSITIVE_TIME!3!1!1!0!0!0!
ISRFELEMENT!1!1!1!1!0!0!
RFELEMENTTYPE!1!1!1!1!0!0!
RFLAYER!1!1!1!1!0!0!
RFLAYER1!1!1!1!1!0!0!
RFLAYER2!1!1!1!1!0!0!
RFLAYER3!1!1!1!1!0!0!
RFLAYER4!1!1!1!1!0!0!
RFLAYER5!1!1!1!1!0!0!
RFLAYER6!1!1!1!1!0!0!
RFLAYER7!1!1!1!1!0!0!
RFLAYER8!1!1!1!1!0!0!
RFLAYER9!1!1!1!1!0!0!
RFLAYER10!1!1!1!1!0!0!
RFLAYER11!1!1!1!1!0!0!
RFLAYER12!1!1!1!1!0!0!
RFLAYER13!1!1!1!1!0!0!
RFLAYER14!1!1!1!1!0!0!
RFLAYER15!1!1!1!1!0!0!
RFLAYER16!1!1!1!1!0!0!
RFCOUPLINGMODE!1!1!1!1!0!0!
RFFLIPMODE!1!1!1!1!0!0!
RFANGLE!1!1!1!1!0!0!
RFANGLE1!1!1!1!1!0!0!
RFWIDTH!1!1!1!1!0!0!
RFWIDTH1!1!1!1!1!0!0!
RFWIDTH2!1!1!1!1!0!0!
RFWIDTH3!1!1!1!1!0!0!
RFWIDTH4!1!1!1!1!0!0!
RFWIDTH5!1!1!1!1!0!0!
RFWIDTH6!1!1!1!1!0!0!
RFWIDTH7!1!1!1!1!0!0!
RFWIDTH8!1!1!1!1!0!0!
RFWIDTH9!1!1!1!1!0!0!
RFWIDTH10!1!1!1!1!0!0!
RFWIDTH11!1!1!1!1!0!0!
RFWIDTH12!1!1!1!1!0!0!
RFWIDTH13!1!1!1!1!0!0!
RFWIDTH14!1!1!1!1!0!0!
RFWIDTH15!1!1!1!1!0!0!
RFWIDTH16!1!1!1!1!0!0!
RFLENGTH!1!1!1!1!0!0!
RFLENGTH1!1!1!1!1!0!0!
RFLENGTH2!1!1!1!1!0!0!
RFLENGTH3!1!1!1!1!0!0!
RFLENGTH4!1!1!1!1!0!0!
RFLENGTH5!1!1!1!1!0!0!
RFLENGTH6!1!1!1!1!0!0!
RFLENGTH7!1!1!1!1!0!0!
RFLENGTH8!1!1!1!1!0!0!
RFSPACING!1!1!1!1!0!0!
RFSPACING1!1!1!1!1!0!0!
RFSPACING2!1!1!1!1!0!0!
RFSPACING3!1!1!1!1!0!0!
RFSPACING4!1!1!1!1!0!0!
RFSPACING5!1!1!1!1!0!0!
RFSPACING6!1!1!1!1!0!0!
RFSPACING7!1!1!1!1!0!0!
RFSPACING8!1!1!1!1!0!0!
RFSPACING9!1!1!1!1!0!0!
RFSPACING10!1!1!1!1!0!0!
RFSPACING11!1!1!1!1!0!0!
RFSPACING12!1!1!1!1!0!0!
RFSPACING13!1!1!1!1!0!0!
RFSPACING14!1!1!1!1!0!0!
RFSPACING15!1!1!1!1!0!0!
RFOFFSETX!1!1!1!1!0!0!
RFOFFSETY!1!1!1!1!0!0!
RFRADIUS!1!1!1!1!0!0!
RFDEPTH!1!1!1!1!0!0!
RFFREQUENCY!1!1!1!1!0!0!
RFMITERFRACTION!1!1!1!1!0!0!
RFBENDMODE!1!1!1!1!0!0!
RFNUMBERLEGS!1!1!1!1!0!0!
RFNUMBERPAIRS!1!1!1!1!0!0!
RFNUMBERTURNS!1!1!1!1!0!0!
RFCAPACITANCE!1!1!1!1!0!0!
RFRESISTANCE!1!1!1!1!0!0!
RFINDUCTANCE!1!1!1!1!0!0!
RFPADSTACKNAME!1!1!1!1!0!0!
RFPADSSMNAME1!1!1!1!1!0!0!
RFPADSSMNAME2!1!1!1!1!0!0!
RFPADBEGINLAYER!1!1!1!1!0!0!
RFPADENDLAYER!1!1!1!1!0!0!
RFPADLINEWIDTH1!1!1!1!1!0!0!
RFPADLINEWIDTH2!1!1!1!1!0!0!
RFPADDIAMETER1!1!1!1!1!0!0!
RFPADDIAMETER2!1!1!1!1!0!0!
RFPADLENGTH1!1!1!1!1!0!0!
RFPADLENGTH2!1!1!1!1!0!0!
RFHOLEDIAMETER!1!1!1!1!0!0!
RFPADANGLE!1!1!1!1!0!0!
RFDRANAME!1!1!1!1!0!0!
RFPADTYPE!1!1!1!1!0!0!
RFBLOCK!1!1!1!1!0!0!
RFDCNET!1!1!1!1!0!0!
RFGROUP!1!1!1!1!0!0!
RFSPLIT!3!1!1!1!0!0!
NO_XNET_CONNECTION!1!1!1!1!0!0!
Reference in New Issue View Git Blame Copy Permalink