Tubii_Tk2/worklib/caen_analog_coms/entity/verilog.v
2015-03-02 19:19:52 -05:00

20 lines
373 B
Verilog

// generated by newgenasym Mon Mar 02 15:14:00 2015
module caen_analog_coms (caen_out_anal, clk, data, data_rdy, le, pulse_in_anal,
scope_out_anal);
output [0:7] caen_out_anal;
input clk;
input data;
input data_rdy;
input le;
input [0:11] pulse_in_anal;
output [0:7] scope_out_anal;
initial
begin
end
endmodule