16 lines
479 B
VHDL
16 lines
479 B
VHDL
-- generated by newgenasym Mon Mar 02 15:14:00 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity caen_analog_coms is
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port (
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CAEN_OUT_ANAL: OUT STD_LOGIC_VECTOR (0 TO 7);
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CLK: IN STD_LOGIC;
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DATA: IN STD_LOGIC;
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DATA_RDY: IN STD_LOGIC;
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LE: IN STD_LOGIC;
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PULSE_IN_ANAL: IN STD_LOGIC_VECTOR (0 TO 11);
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SCOPE_OUT_ANAL: OUT STD_LOGIC_VECTOR (0 TO 7));
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end caen_analog_coms;
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