14 lines
339 B
VHDL
14 lines
339 B
VHDL
-- generated by newgenasym Tue May 12 17:59:41 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity CAEN_BUFFER is
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port (
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CNTRL: IN std_logic;
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IN_ANAL: IN std_logic;
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OUT_ATT: OUT std_logic;
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OUT_CLIP: OUT std_logic;
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VREF5M: IN std_logic);
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end CAEN_BUFFER;
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