37 lines
1.6 KiB
CSS
37 lines
1.6 KiB
CSS
L -275 200 275 200 -1 16
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L -275 -100 275 -100 -1 16
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L 275 300 -275 300 -1 16
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L -325 -75 -275 -75 -1 16
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L -325 25 -275 25 -1 16
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L -275 -100 -275 300 -1 16
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L -325 100 -275 100 -1 16
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L 325 125 275 125 -1 16
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L 275 -100 275 300 -1 16
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L 325 0 275 0 -1 16
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T 0 240 0.00 0.00 47 0 0 1 0 11 0
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CAEN_BUFFER
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C 325 0 "OUT_ATT" 345 -23 0 1 47 0 L
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X "VHDL_MODE" "out" 345 -67 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "OUT_ATT" 265 -23 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "VHDL_SCALAR_TYPE" "std_logic" 345 -149 0.00 0.00 20 0 0 0 0 0 0 0 126
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C 325 125 "OUT_CLIP" 345 102 0 1 47 0 L
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X "VHDL_MODE" "out" 345 58 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "OUT_CLIP" 265 102 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "VHDL_SCALAR_TYPE" "std_logic" 345 -24 0.00 0.00 20 0 0 0 0 0 0 0 126
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C -325 100 "CNTRL" -345 77 0 1 47 0 R
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X "VHDL_MODE" "in" -345 33 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "PIN_TEXT" "CNTRL" -265 77 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "VHDL_SCALAR_TYPE" "std_logic" -345 -49 0.00 0.00 20 0 0 0 0 0 0 0 126
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C -325 25 "IN_ANAL" -345 2 0 1 47 0 R
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X "VHDL_MODE" "in" -345 -42 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "PIN_TEXT" "IN_ANAL" -265 2 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "VHDL_SCALAR_TYPE" "std_logic" -345 -124 0.00 0.00 20 0 0 0 0 0 0 0 126
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C -325 -75 "VREF5M" -345 -98 0 1 47 0 R
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X "VHDL_MODE" "in" -345 -142 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "PIN_TEXT" "VREF5M" -265 -98 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "VHDL_SCALAR_TYPE" "std_logic" -345 -224 0.00 0.00 20 0 0 0 0 0 0 0 126
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P "USE2" "work.all" 436 294 0.00 0.00 20 0 0 0 0 0 0 0 72
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P "USE1" "ieee.std_logic_1164.all" 436 314 0.00 0.00 20 0 0 0 0 0 0 0 72
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P "LIBRARY1" "ieee" 436 335 0.00 0.00 20 0 0 0 0 0 0 0 72
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P "BLOCK" "TRUE" 0 10 0.00 0.00 47 0 0 1 0 0 0 0 99
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