Tubii_Tk2/worklib/caen_coms/entity/verilog.v
2015-05-18 16:11:03 -04:00

40 lines
907 B
Verilog

// generated by newgenasym Mon May 18 15:57:28 2015
module caen_coms (caen_out_anal, clk, data, data_rdy, gt2_n, gt2_p, gt_n,
gt_nim, gt_p, gt_ttl, gt_ttl_out, le, pulse_in_anal,
scope_out_anal, sync24_lvds_n, sync24_lvds_p, sync24_n,
sync24_p, sync24_ttl, sync_lvds_n, sync_lvds_p, sync_n,
sync_p, sync_ttl);
output [0:7] caen_out_anal;
input clk;
input data;
input data_rdy;
output gt2_n;
output gt2_p;
input gt_n;
output gt_nim;
input gt_p;
output gt_ttl;
output gt_ttl_out;
input le;
input [0:11] pulse_in_anal;
output [0:7] scope_out_anal;
output sync24_lvds_n;
output sync24_lvds_p;
input sync24_n;
input sync24_p;
output sync24_ttl;
output sync_lvds_n;
output sync_lvds_p;
input sync_n;
input sync_p;
output sync_ttl;
initial
begin
end
endmodule