33 lines
1.0 KiB
VHDL
33 lines
1.0 KiB
VHDL
-- generated by newgenasym Mon May 18 15:57:28 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity caen_coms is
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port (
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CAEN_OUT_ANAL: OUT STD_LOGIC_VECTOR (0 TO 7);
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CLK: IN STD_LOGIC;
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DATA: IN STD_LOGIC;
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DATA_RDY: IN STD_LOGIC;
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GT2_N: OUT STD_LOGIC;
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GT2_P: OUT STD_LOGIC;
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GT_N: IN STD_LOGIC;
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GT_NIM: OUT STD_LOGIC;
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GT_P: IN STD_LOGIC;
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GT_TTL: OUT STD_LOGIC;
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GT_TTL_OUT: OUT STD_LOGIC;
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LE: IN STD_LOGIC;
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PULSE_IN_ANAL: IN STD_LOGIC_VECTOR (0 TO 11);
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SCOPE_OUT_ANAL: OUT STD_LOGIC_VECTOR (0 TO 7);
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SYNC24_LVDS_N: OUT STD_LOGIC;
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SYNC24_LVDS_P: OUT STD_LOGIC;
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SYNC24_N: IN STD_LOGIC;
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SYNC24_P: IN STD_LOGIC;
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SYNC24_TTL: OUT STD_LOGIC;
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SYNC_LVDS_N: OUT STD_LOGIC;
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SYNC_LVDS_P: OUT STD_LOGIC;
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SYNC_N: IN STD_LOGIC;
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SYNC_P: IN STD_LOGIC;
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SYNC_TTL: OUT STD_LOGIC);
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end caen_coms;
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