1037 lines
23 KiB
Plaintext
1037 lines
23 KiB
Plaintext
FILE_TYPE = MACRO_DRAWING;
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SET COLOR_WIRE YELLOW;
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SET COLOR_PROP MONO;
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SET COLOR_DOT WHITE;
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SET COLOR_ARC YELLOW;
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SET COLOR_BODY GREEN;
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SET COLOR_NOTE MONO;
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SET PROP_DISPLAY VALUE;
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SET PAGE_NUMBER P1;
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FORCEADD CAEN_ANALOG_COMS..1
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(-375 2200);
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FORCEPROP 2 LAST PATH I1
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J 0
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(0 2750);
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DISPLAY 1.021277 (0 2750);
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PAINT ORANGE (0 2750);
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FORCEPROP 1 LASTPIN (-925 1925) VHDL_MODE IN
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J 2
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(-945 1858);
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DISPLAY INVISIBLE (-945 1858);
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FORCEPROP 1 LASTPIN (-925 2000) VHDL_MODE IN
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J 2
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(-945 1933);
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DISPLAY INVISIBLE (-945 1933);
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FORCEPROP 1 LASTPIN (-925 2100) VHDL_MODE IN
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J 2
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(-945 2033);
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DISPLAY INVISIBLE (-945 2033);
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FORCEPROP 1 LASTPIN (-925 2175) VHDL_MODE IN
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J 2
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(-945 2108);
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DISPLAY INVISIBLE (-945 2108);
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FORCEPROP 1 LASTPIN (-925 2525) VHDL_MODE IN
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J 2
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(-945 2458);
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DISPLAY INVISIBLE (-945 2458);
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FORCEPROP 1 LASTPIN (150 2300) VHDL_MODE OUT
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J 0
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(170 2233);
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DISPLAY INVISIBLE (170 2233);
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FORCEPROP 1 LASTPIN (150 2425) VHDL_MODE OUT
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J 0
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(170 2358);
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DISPLAY INVISIBLE (170 2358);
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FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
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J 0
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(-375 2200);
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DISPLAY INVISIBLE (-375 2200);
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FORCEPROP 1 LAST BLOCK TRUE
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J 1
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(-375 2210);
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DISPLAY INVISIBLE (-375 2210);
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FORCEADD INPORT..1
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(-1450 2175);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(-1125 2050);
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DISPLAY 0.872340 (-1125 2050);
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PAINT ORANGE (-1125 2050);
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DISPLAY INVISIBLE (-1125 2050);
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FORCEPROP 1 LASTPIN (-1400 2175) HDL_PORT IN
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J 0
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(-1125 2050);
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DISPLAY 0.872340 (-1125 2050);
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PAINT ORANGE (-1125 2050);
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DISPLAY INVISIBLE (-1125 2050);
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FORCEPROP 1 LASTPIN (-1400 2175) VHDL_PORT IN
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J 0
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(-1385 2105);
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DISPLAY 0.872340 (-1385 2105);
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PAINT PINK (-1385 2105);
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DISPLAY INVISIBLE (-1385 2105);
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FORCEPROP 1 LAST PATH I10
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J 0
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(-1475 2225);
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DISPLAY 0.872340 (-1475 2225);
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PAINT PINK (-1475 2225);
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DISPLAY INVISIBLE (-1475 2225);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(-1450 2175);
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DISPLAY INVISIBLE (-1450 2175);
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FORCEADD INPORT..1
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(-1450 2100);
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FORCEPROP 1 LASTPIN (-1400 2100) VHDL_PORT IN
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J 0
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(-1385 2030);
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DISPLAY 0.872340 (-1385 2030);
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PAINT PINK (-1385 2030);
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DISPLAY INVISIBLE (-1385 2030);
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FORCEPROP 1 LASTPIN (-1400 2100) HDL_PORT IN
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J 0
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(-1125 1975);
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DISPLAY 0.872340 (-1125 1975);
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PAINT ORANGE (-1125 1975);
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DISPLAY INVISIBLE (-1125 1975);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(-1125 1975);
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DISPLAY 0.872340 (-1125 1975);
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PAINT ORANGE (-1125 1975);
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DISPLAY INVISIBLE (-1125 1975);
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FORCEPROP 1 LAST PATH I11
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J 0
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(-1475 2150);
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DISPLAY 0.872340 (-1475 2150);
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PAINT PINK (-1475 2150);
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DISPLAY INVISIBLE (-1475 2150);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(-1450 2100);
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DISPLAY INVISIBLE (-1450 2100);
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FORCEADD INPORT..1
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(-1450 2000);
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FORCEPROP 1 LASTPIN (-1400 2000) VHDL_PORT IN
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J 0
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(-1385 1930);
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DISPLAY 0.872340 (-1385 1930);
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PAINT PINK (-1385 1930);
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DISPLAY INVISIBLE (-1385 1930);
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FORCEPROP 1 LASTPIN (-1400 2000) HDL_PORT IN
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J 0
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(-1125 1875);
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DISPLAY 0.872340 (-1125 1875);
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PAINT ORANGE (-1125 1875);
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DISPLAY INVISIBLE (-1125 1875);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(-1125 1875);
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DISPLAY 0.872340 (-1125 1875);
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PAINT ORANGE (-1125 1875);
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DISPLAY INVISIBLE (-1125 1875);
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FORCEPROP 1 LAST PATH I12
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J 0
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(-1475 2050);
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DISPLAY 0.872340 (-1475 2050);
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PAINT PINK (-1475 2050);
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DISPLAY INVISIBLE (-1475 2050);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(-1450 2000);
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DISPLAY INVISIBLE (-1450 2000);
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FORCEADD INPORT..1
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(-1450 1925);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(-1450 1925);
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DISPLAY INVISIBLE (-1450 1925);
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FORCEPROP 1 LAST PATH I13
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J 0
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(-1475 1975);
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DISPLAY 0.872340 (-1475 1975);
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PAINT PINK (-1475 1975);
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DISPLAY INVISIBLE (-1475 1975);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(-1125 1800);
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DISPLAY 0.872340 (-1125 1800);
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PAINT ORANGE (-1125 1800);
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DISPLAY INVISIBLE (-1125 1800);
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FORCEPROP 1 LASTPIN (-1400 1925) HDL_PORT IN
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J 0
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(-1125 1800);
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DISPLAY 0.872340 (-1125 1800);
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PAINT ORANGE (-1125 1800);
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DISPLAY INVISIBLE (-1125 1800);
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FORCEPROP 1 LASTPIN (-1400 1925) VHDL_PORT IN
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J 0
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(-1385 1855);
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DISPLAY 0.872340 (-1385 1855);
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PAINT PINK (-1385 1855);
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DISPLAY INVISIBLE (-1385 1855);
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FORCEADD OUTPORT..1
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(975 4025);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(975 4025);
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DISPLAY INVISIBLE (975 4025);
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FORCEPROP 1 LAST PATH I14
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J 0
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(975 4075);
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DISPLAY 0.872340 (975 4075);
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PAINT PINK (975 4075);
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DISPLAY INVISIBLE (975 4075);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(1300 3900);
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DISPLAY 0.872340 (1300 3900);
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PAINT ORANGE (1300 3900);
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DISPLAY INVISIBLE (1300 3900);
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FORCEPROP 1 LASTPIN (925 4025) HDL_PORT OUT
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J 0
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(1300 3900);
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DISPLAY 0.872340 (1300 3900);
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PAINT ORANGE (1300 3900);
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DISPLAY INVISIBLE (1300 3900);
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FORCEPROP 1 LASTPIN (925 4025) VHDL_PORT OUT
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|
J 0
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|
(940 3955);
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DISPLAY 0.872340 (940 3955);
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PAINT PINK (940 3955);
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DISPLAY INVISIBLE (940 3955);
|
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FORCEADD OUTPORT..1
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|
(975 3950);
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FORCEPROP 1 LASTPIN (925 3950) VHDL_PORT OUT
|
|
J 0
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(940 3880);
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DISPLAY 0.872340 (940 3880);
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PAINT PINK (940 3880);
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DISPLAY INVISIBLE (940 3880);
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FORCEPROP 1 LASTPIN (925 3950) HDL_PORT OUT
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|
J 0
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(1300 3825);
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DISPLAY 0.872340 (1300 3825);
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PAINT ORANGE (1300 3825);
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DISPLAY INVISIBLE (1300 3825);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(1300 3825);
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DISPLAY 0.872340 (1300 3825);
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PAINT ORANGE (1300 3825);
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DISPLAY INVISIBLE (1300 3825);
|
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FORCEPROP 1 LAST PATH I15
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J 0
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(975 4000);
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DISPLAY 0.872340 (975 4000);
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PAINT PINK (975 4000);
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DISPLAY INVISIBLE (975 4000);
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FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
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(975 3950);
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DISPLAY INVISIBLE (975 3950);
|
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FORCEADD OUTPORT..1
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(975 3800);
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FORCEPROP 1 LASTPIN (925 3800) VHDL_PORT OUT
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J 0
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(940 3730);
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DISPLAY 0.872340 (940 3730);
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PAINT PINK (940 3730);
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DISPLAY INVISIBLE (940 3730);
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FORCEPROP 1 LASTPIN (925 3800) HDL_PORT OUT
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|
J 0
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(1300 3675);
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DISPLAY 0.872340 (1300 3675);
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PAINT ORANGE (1300 3675);
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DISPLAY INVISIBLE (1300 3675);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(1300 3675);
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DISPLAY 0.872340 (1300 3675);
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PAINT ORANGE (1300 3675);
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DISPLAY INVISIBLE (1300 3675);
|
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FORCEPROP 1 LAST PATH I16
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J 0
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(975 3850);
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DISPLAY 0.872340 (975 3850);
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PAINT PINK (975 3850);
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DISPLAY INVISIBLE (975 3850);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
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|
(975 3800);
|
|
DISPLAY INVISIBLE (975 3800);
|
|
FORCEADD OUTPORT..1
|
|
(975 3725);
|
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FORCEPROP 1 LASTPIN (925 3725) VHDL_PORT OUT
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|
J 0
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|
(940 3655);
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DISPLAY 0.872340 (940 3655);
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PAINT PINK (940 3655);
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DISPLAY INVISIBLE (940 3655);
|
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FORCEPROP 1 LASTPIN (925 3725) HDL_PORT OUT
|
|
J 0
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|
(1300 3600);
|
|
DISPLAY 0.872340 (1300 3600);
|
|
PAINT ORANGE (1300 3600);
|
|
DISPLAY INVISIBLE (1300 3600);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
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|
(1300 3600);
|
|
DISPLAY 0.872340 (1300 3600);
|
|
PAINT ORANGE (1300 3600);
|
|
DISPLAY INVISIBLE (1300 3600);
|
|
FORCEPROP 1 LAST PATH I17
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|
J 0
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|
(975 3775);
|
|
DISPLAY 0.872340 (975 3775);
|
|
PAINT PINK (975 3775);
|
|
DISPLAY INVISIBLE (975 3775);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(975 3725);
|
|
DISPLAY INVISIBLE (975 3725);
|
|
FORCEADD OUTPORT..1
|
|
(1000 3600);
|
|
FORCEPROP 1 LASTPIN (950 3600) VHDL_PORT OUT
|
|
J 0
|
|
(965 3530);
|
|
DISPLAY 0.872340 (965 3530);
|
|
PAINT PINK (965 3530);
|
|
DISPLAY INVISIBLE (965 3530);
|
|
FORCEPROP 1 LASTPIN (950 3600) HDL_PORT OUT
|
|
J 0
|
|
(1325 3475);
|
|
DISPLAY 0.872340 (1325 3475);
|
|
PAINT ORANGE (1325 3475);
|
|
DISPLAY INVISIBLE (1325 3475);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1325 3475);
|
|
DISPLAY 0.872340 (1325 3475);
|
|
PAINT ORANGE (1325 3475);
|
|
DISPLAY INVISIBLE (1325 3475);
|
|
FORCEPROP 1 LAST PATH I18
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J 0
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|
(1000 3650);
|
|
DISPLAY 0.872340 (1000 3650);
|
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PAINT PINK (1000 3650);
|
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DISPLAY INVISIBLE (1000 3650);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
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|
(1000 3600);
|
|
DISPLAY INVISIBLE (1000 3600);
|
|
FORCEADD OUTPORT..1
|
|
(825 2425);
|
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FORCEPROP 1 LASTPIN (775 2425) VHDL_PORT OUT
|
|
J 0
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|
(790 2355);
|
|
DISPLAY 0.872340 (790 2355);
|
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PAINT PINK (790 2355);
|
|
DISPLAY INVISIBLE (790 2355);
|
|
FORCEPROP 1 LASTPIN (775 2425) HDL_PORT OUT
|
|
J 0
|
|
(1150 2300);
|
|
DISPLAY 0.872340 (1150 2300);
|
|
PAINT ORANGE (1150 2300);
|
|
DISPLAY INVISIBLE (1150 2300);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1150 2300);
|
|
DISPLAY 0.872340 (1150 2300);
|
|
PAINT ORANGE (1150 2300);
|
|
DISPLAY INVISIBLE (1150 2300);
|
|
FORCEPROP 1 LAST PATH I19
|
|
J 0
|
|
(825 2475);
|
|
DISPLAY 0.872340 (825 2475);
|
|
PAINT PINK (825 2475);
|
|
DISPLAY INVISIBLE (825 2475);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
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|
(825 2425);
|
|
DISPLAY INVISIBLE (825 2425);
|
|
FORCEADD CAEN_DIG_COMS..1
|
|
(-275 3500);
|
|
FORCEPROP 1 LASTPIN (275 3475) VHDL_MODE OUT
|
|
J 0
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(295 3408);
|
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DISPLAY INVISIBLE (295 3408);
|
|
FORCEPROP 2 LAST PATH I2
|
|
J 0
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|
(325 4300);
|
|
DISPLAY 1.021277 (325 4300);
|
|
PAINT ORANGE (325 4300);
|
|
FORCEPROP 1 LASTPIN (275 3350) VHDL_MODE OUT
|
|
J 0
|
|
(295 3283);
|
|
DISPLAY INVISIBLE (295 3283);
|
|
FORCEPROP 1 LASTPIN (275 3425) VHDL_MODE OUT
|
|
J 0
|
|
(295 3358);
|
|
DISPLAY INVISIBLE (295 3358);
|
|
FORCEPROP 1 LASTPIN (275 3525) VHDL_MODE OUT
|
|
J 0
|
|
(295 3458);
|
|
DISPLAY INVISIBLE (295 3458);
|
|
FORCEPROP 1 LASTPIN (275 3600) VHDL_MODE OUT
|
|
J 0
|
|
(295 3533);
|
|
DISPLAY INVISIBLE (295 3533);
|
|
FORCEPROP 1 LASTPIN (275 3950) VHDL_MODE OUT
|
|
J 0
|
|
(295 3883);
|
|
DISPLAY INVISIBLE (295 3883);
|
|
FORCEPROP 1 LASTPIN (275 4025) VHDL_MODE OUT
|
|
J 0
|
|
(295 3958);
|
|
DISPLAY INVISIBLE (295 3958);
|
|
FORCEPROP 1 LASTPIN (275 3725) VHDL_MODE OUT
|
|
J 0
|
|
(295 3658);
|
|
DISPLAY INVISIBLE (295 3658);
|
|
FORCEPROP 1 LASTPIN (275 3800) VHDL_MODE OUT
|
|
J 0
|
|
(295 3733);
|
|
DISPLAY INVISIBLE (295 3733);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(-275 3510);
|
|
DISPLAY INVISIBLE (-275 3510);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(-275 3500);
|
|
DISPLAY INVISIBLE (-275 3500);
|
|
FORCEPROP 1 LASTPIN (-1025 4000) VHDL_MODE IN
|
|
J 2
|
|
(-1045 3933);
|
|
DISPLAY INVISIBLE (-1045 3933);
|
|
FORCEPROP 1 LASTPIN (-1025 3925) VHDL_MODE IN
|
|
J 2
|
|
(-1045 3858);
|
|
DISPLAY INVISIBLE (-1045 3858);
|
|
FORCEPROP 1 LASTPIN (-1025 3800) VHDL_MODE IN
|
|
J 2
|
|
(-1045 3733);
|
|
DISPLAY INVISIBLE (-1045 3733);
|
|
FORCEPROP 1 LASTPIN (-1025 3725) VHDL_MODE IN
|
|
J 2
|
|
(-1045 3658);
|
|
DISPLAY INVISIBLE (-1045 3658);
|
|
FORCEPROP 1 LASTPIN (-1025 3600) VHDL_MODE IN
|
|
J 2
|
|
(-1045 3533);
|
|
DISPLAY INVISIBLE (-1045 3533);
|
|
FORCEPROP 1 LASTPIN (-1025 3525) VHDL_MODE IN
|
|
J 2
|
|
(-1045 3458);
|
|
DISPLAY INVISIBLE (-1045 3458);
|
|
FORCEPROP 1 LASTPIN (275 4225) VHDL_MODE OUT
|
|
J 0
|
|
(295 4158);
|
|
DISPLAY INVISIBLE (295 4158);
|
|
FORCEPROP 1 LASTPIN (275 4325) VHDL_MODE OUT
|
|
J 0
|
|
(295 4258);
|
|
DISPLAY INVISIBLE (295 4258);
|
|
FORCEADD OUTPORT..1
|
|
(825 2300);
|
|
FORCEPROP 1 LASTPIN (775 2300) VHDL_PORT OUT
|
|
J 0
|
|
(790 2230);
|
|
DISPLAY 0.872340 (790 2230);
|
|
PAINT PINK (790 2230);
|
|
DISPLAY INVISIBLE (790 2230);
|
|
FORCEPROP 1 LASTPIN (775 2300) HDL_PORT OUT
|
|
J 0
|
|
(1150 2175);
|
|
DISPLAY 0.872340 (1150 2175);
|
|
PAINT ORANGE (1150 2175);
|
|
DISPLAY INVISIBLE (1150 2175);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1150 2175);
|
|
DISPLAY 0.872340 (1150 2175);
|
|
PAINT ORANGE (1150 2175);
|
|
DISPLAY INVISIBLE (1150 2175);
|
|
FORCEPROP 1 LAST PATH I20
|
|
J 0
|
|
(825 2350);
|
|
DISPLAY 0.872340 (825 2350);
|
|
PAINT PINK (825 2350);
|
|
DISPLAY INVISIBLE (825 2350);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(825 2300);
|
|
DISPLAY INVISIBLE (825 2300);
|
|
FORCEADD OUTPORT..1
|
|
(1000 3525);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(1000 3525);
|
|
DISPLAY INVISIBLE (1000 3525);
|
|
FORCEPROP 1 LAST PATH I21
|
|
J 0
|
|
(1000 3575);
|
|
DISPLAY 0.872340 (1000 3575);
|
|
PAINT PINK (1000 3575);
|
|
DISPLAY INVISIBLE (1000 3575);
|
|
FORCEPROP 1 LASTPIN (950 3525) VHDL_PORT OUT
|
|
J 0
|
|
(965 3455);
|
|
DISPLAY 0.872340 (965 3455);
|
|
PAINT PINK (965 3455);
|
|
DISPLAY INVISIBLE (965 3455);
|
|
FORCEPROP 1 LASTPIN (950 3525) HDL_PORT OUT
|
|
J 0
|
|
(1325 3400);
|
|
DISPLAY 0.872340 (1325 3400);
|
|
PAINT ORANGE (1325 3400);
|
|
DISPLAY INVISIBLE (1325 3400);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1325 3400);
|
|
DISPLAY 0.872340 (1325 3400);
|
|
PAINT ORANGE (1325 3400);
|
|
DISPLAY INVISIBLE (1325 3400);
|
|
FORCEADD OUTPORT..1
|
|
(1000 3425);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1325 3300);
|
|
DISPLAY 0.872340 (1325 3300);
|
|
PAINT ORANGE (1325 3300);
|
|
DISPLAY INVISIBLE (1325 3300);
|
|
FORCEPROP 1 LASTPIN (950 3425) HDL_PORT OUT
|
|
J 0
|
|
(1325 3300);
|
|
DISPLAY 0.872340 (1325 3300);
|
|
PAINT ORANGE (1325 3300);
|
|
DISPLAY INVISIBLE (1325 3300);
|
|
FORCEPROP 1 LASTPIN (950 3425) VHDL_PORT OUT
|
|
J 0
|
|
(965 3355);
|
|
DISPLAY 0.872340 (965 3355);
|
|
PAINT PINK (965 3355);
|
|
DISPLAY INVISIBLE (965 3355);
|
|
FORCEPROP 1 LAST PATH I22
|
|
J 0
|
|
(1000 3475);
|
|
DISPLAY 0.872340 (1000 3475);
|
|
PAINT PINK (1000 3475);
|
|
DISPLAY INVISIBLE (1000 3475);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(1000 3425);
|
|
DISPLAY INVISIBLE (1000 3425);
|
|
FORCEADD OUTPORT..1
|
|
(1000 3350);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1325 3225);
|
|
DISPLAY 0.872340 (1325 3225);
|
|
PAINT ORANGE (1325 3225);
|
|
DISPLAY INVISIBLE (1325 3225);
|
|
FORCEPROP 1 LASTPIN (950 3350) HDL_PORT OUT
|
|
J 0
|
|
(1325 3225);
|
|
DISPLAY 0.872340 (1325 3225);
|
|
PAINT ORANGE (1325 3225);
|
|
DISPLAY INVISIBLE (1325 3225);
|
|
FORCEPROP 1 LASTPIN (950 3350) VHDL_PORT OUT
|
|
J 0
|
|
(965 3280);
|
|
DISPLAY 0.872340 (965 3280);
|
|
PAINT PINK (965 3280);
|
|
DISPLAY INVISIBLE (965 3280);
|
|
FORCEPROP 1 LAST PATH I23
|
|
J 0
|
|
(1000 3400);
|
|
DISPLAY 0.872340 (1000 3400);
|
|
PAINT PINK (1000 3400);
|
|
DISPLAY INVISIBLE (1000 3400);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(1000 3350);
|
|
DISPLAY INVISIBLE (1000 3350);
|
|
FORCEADD OUTPORT..1
|
|
(950 4325);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1275 4200);
|
|
DISPLAY 0.872340 (1275 4200);
|
|
PAINT ORANGE (1275 4200);
|
|
DISPLAY INVISIBLE (1275 4200);
|
|
FORCEPROP 1 LASTPIN (900 4325) HDL_PORT OUT
|
|
J 0
|
|
(1275 4200);
|
|
DISPLAY 0.872340 (1275 4200);
|
|
PAINT ORANGE (1275 4200);
|
|
DISPLAY INVISIBLE (1275 4200);
|
|
FORCEPROP 1 LASTPIN (900 4325) VHDL_PORT OUT
|
|
J 0
|
|
(915 4255);
|
|
DISPLAY 0.872340 (915 4255);
|
|
PAINT PINK (915 4255);
|
|
DISPLAY INVISIBLE (915 4255);
|
|
FORCEPROP 1 LAST PATH I24
|
|
J 0
|
|
(950 4375);
|
|
DISPLAY 0.872340 (950 4375);
|
|
PAINT PINK (950 4375);
|
|
DISPLAY INVISIBLE (950 4375);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(950 4325);
|
|
DISPLAY INVISIBLE (950 4325);
|
|
FORCEADD OUTPORT..1
|
|
(950 4225);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1275 4100);
|
|
DISPLAY 0.872340 (1275 4100);
|
|
PAINT ORANGE (1275 4100);
|
|
DISPLAY INVISIBLE (1275 4100);
|
|
FORCEPROP 1 LASTPIN (900 4225) HDL_PORT OUT
|
|
J 0
|
|
(1275 4100);
|
|
DISPLAY 0.872340 (1275 4100);
|
|
PAINT ORANGE (1275 4100);
|
|
DISPLAY INVISIBLE (1275 4100);
|
|
FORCEPROP 1 LASTPIN (900 4225) VHDL_PORT OUT
|
|
J 0
|
|
(915 4155);
|
|
DISPLAY 0.872340 (915 4155);
|
|
PAINT PINK (915 4155);
|
|
DISPLAY INVISIBLE (915 4155);
|
|
FORCEPROP 1 LAST PATH I25
|
|
J 0
|
|
(950 4275);
|
|
DISPLAY 0.872340 (950 4275);
|
|
PAINT PINK (950 4275);
|
|
DISPLAY INVISIBLE (950 4275);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(950 4225);
|
|
DISPLAY INVISIBLE (950 4225);
|
|
FORCEADD OUTPORT..1
|
|
(1000 3475);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(1000 3475);
|
|
DISPLAY INVISIBLE (1000 3475);
|
|
FORCEPROP 1 LAST PATH I26
|
|
J 0
|
|
(1000 3525);
|
|
DISPLAY 0.872340 (1000 3525);
|
|
PAINT PINK (1000 3525);
|
|
DISPLAY INVISIBLE (1000 3525);
|
|
FORCEPROP 1 LASTPIN (950 3475) VHDL_PORT OUT
|
|
J 0
|
|
(965 3405);
|
|
DISPLAY 0.872340 (965 3405);
|
|
PAINT PINK (965 3405);
|
|
DISPLAY INVISIBLE (965 3405);
|
|
FORCEPROP 1 LASTPIN (950 3475) HDL_PORT OUT
|
|
J 0
|
|
(1325 3350);
|
|
DISPLAY 0.872340 (1325 3350);
|
|
PAINT ORANGE (1325 3350);
|
|
DISPLAY INVISIBLE (1325 3350);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1325 3350);
|
|
DISPLAY 0.872340 (1325 3350);
|
|
PAINT ORANGE (1325 3350);
|
|
DISPLAY INVISIBLE (1325 3350);
|
|
FORCEADD INPORT..1
|
|
(-1550 4000);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1550 4000);
|
|
DISPLAY INVISIBLE (-1550 4000);
|
|
FORCEPROP 1 LAST PATH I3
|
|
J 0
|
|
(-1575 4050);
|
|
DISPLAY 0.872340 (-1575 4050);
|
|
PAINT PINK (-1575 4050);
|
|
DISPLAY INVISIBLE (-1575 4050);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1225 3875);
|
|
DISPLAY 0.872340 (-1225 3875);
|
|
PAINT ORANGE (-1225 3875);
|
|
DISPLAY INVISIBLE (-1225 3875);
|
|
FORCEPROP 1 LASTPIN (-1500 4000) HDL_PORT IN
|
|
J 0
|
|
(-1225 3875);
|
|
DISPLAY 0.872340 (-1225 3875);
|
|
PAINT ORANGE (-1225 3875);
|
|
DISPLAY INVISIBLE (-1225 3875);
|
|
FORCEPROP 1 LASTPIN (-1500 4000) VHDL_PORT IN
|
|
J 0
|
|
(-1485 3930);
|
|
DISPLAY 0.872340 (-1485 3930);
|
|
PAINT PINK (-1485 3930);
|
|
DISPLAY INVISIBLE (-1485 3930);
|
|
FORCEADD INPORT..1
|
|
(-1550 3925);
|
|
FORCEPROP 1 LASTPIN (-1500 3925) VHDL_PORT IN
|
|
J 0
|
|
(-1485 3855);
|
|
DISPLAY 0.872340 (-1485 3855);
|
|
PAINT PINK (-1485 3855);
|
|
DISPLAY INVISIBLE (-1485 3855);
|
|
FORCEPROP 1 LASTPIN (-1500 3925) HDL_PORT IN
|
|
J 0
|
|
(-1225 3800);
|
|
DISPLAY 0.872340 (-1225 3800);
|
|
PAINT ORANGE (-1225 3800);
|
|
DISPLAY INVISIBLE (-1225 3800);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1225 3800);
|
|
DISPLAY 0.872340 (-1225 3800);
|
|
PAINT ORANGE (-1225 3800);
|
|
DISPLAY INVISIBLE (-1225 3800);
|
|
FORCEPROP 1 LAST PATH I4
|
|
J 0
|
|
(-1575 3975);
|
|
DISPLAY 0.872340 (-1575 3975);
|
|
PAINT PINK (-1575 3975);
|
|
DISPLAY INVISIBLE (-1575 3975);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1550 3925);
|
|
DISPLAY INVISIBLE (-1550 3925);
|
|
FORCEADD INPORT..1
|
|
(-1550 3800);
|
|
FORCEPROP 1 LASTPIN (-1500 3800) VHDL_PORT IN
|
|
J 0
|
|
(-1485 3730);
|
|
DISPLAY 0.872340 (-1485 3730);
|
|
PAINT PINK (-1485 3730);
|
|
DISPLAY INVISIBLE (-1485 3730);
|
|
FORCEPROP 1 LASTPIN (-1500 3800) HDL_PORT IN
|
|
J 0
|
|
(-1225 3675);
|
|
DISPLAY 0.872340 (-1225 3675);
|
|
PAINT ORANGE (-1225 3675);
|
|
DISPLAY INVISIBLE (-1225 3675);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1225 3675);
|
|
DISPLAY 0.872340 (-1225 3675);
|
|
PAINT ORANGE (-1225 3675);
|
|
DISPLAY INVISIBLE (-1225 3675);
|
|
FORCEPROP 1 LAST PATH I5
|
|
J 0
|
|
(-1575 3850);
|
|
DISPLAY 0.872340 (-1575 3850);
|
|
PAINT PINK (-1575 3850);
|
|
DISPLAY INVISIBLE (-1575 3850);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1550 3800);
|
|
DISPLAY INVISIBLE (-1550 3800);
|
|
FORCEADD INPORT..1
|
|
(-1550 3725);
|
|
FORCEPROP 1 LASTPIN (-1500 3725) VHDL_PORT IN
|
|
J 0
|
|
(-1485 3655);
|
|
DISPLAY 0.872340 (-1485 3655);
|
|
PAINT PINK (-1485 3655);
|
|
DISPLAY INVISIBLE (-1485 3655);
|
|
FORCEPROP 1 LASTPIN (-1500 3725) HDL_PORT IN
|
|
J 0
|
|
(-1225 3600);
|
|
DISPLAY 0.872340 (-1225 3600);
|
|
PAINT ORANGE (-1225 3600);
|
|
DISPLAY INVISIBLE (-1225 3600);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1225 3600);
|
|
DISPLAY 0.872340 (-1225 3600);
|
|
PAINT ORANGE (-1225 3600);
|
|
DISPLAY INVISIBLE (-1225 3600);
|
|
FORCEPROP 1 LAST PATH I6
|
|
J 0
|
|
(-1575 3775);
|
|
DISPLAY 0.872340 (-1575 3775);
|
|
PAINT PINK (-1575 3775);
|
|
DISPLAY INVISIBLE (-1575 3775);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1550 3725);
|
|
DISPLAY INVISIBLE (-1550 3725);
|
|
FORCEADD INPORT..1
|
|
(-1550 3600);
|
|
FORCEPROP 1 LASTPIN (-1500 3600) VHDL_PORT IN
|
|
J 0
|
|
(-1485 3530);
|
|
DISPLAY 0.872340 (-1485 3530);
|
|
PAINT PINK (-1485 3530);
|
|
DISPLAY INVISIBLE (-1485 3530);
|
|
FORCEPROP 1 LASTPIN (-1500 3600) HDL_PORT IN
|
|
J 0
|
|
(-1225 3475);
|
|
DISPLAY 0.872340 (-1225 3475);
|
|
PAINT ORANGE (-1225 3475);
|
|
DISPLAY INVISIBLE (-1225 3475);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1225 3475);
|
|
DISPLAY 0.872340 (-1225 3475);
|
|
PAINT ORANGE (-1225 3475);
|
|
DISPLAY INVISIBLE (-1225 3475);
|
|
FORCEPROP 1 LAST PATH I7
|
|
J 0
|
|
(-1575 3650);
|
|
DISPLAY 0.872340 (-1575 3650);
|
|
PAINT PINK (-1575 3650);
|
|
DISPLAY INVISIBLE (-1575 3650);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1550 3600);
|
|
DISPLAY INVISIBLE (-1550 3600);
|
|
FORCEADD INPORT..1
|
|
(-1550 3525);
|
|
FORCEPROP 1 LASTPIN (-1500 3525) VHDL_PORT IN
|
|
J 0
|
|
(-1485 3455);
|
|
DISPLAY 0.872340 (-1485 3455);
|
|
PAINT PINK (-1485 3455);
|
|
DISPLAY INVISIBLE (-1485 3455);
|
|
FORCEPROP 1 LASTPIN (-1500 3525) HDL_PORT IN
|
|
J 0
|
|
(-1225 3400);
|
|
DISPLAY 0.872340 (-1225 3400);
|
|
PAINT ORANGE (-1225 3400);
|
|
DISPLAY INVISIBLE (-1225 3400);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1225 3400);
|
|
DISPLAY 0.872340 (-1225 3400);
|
|
PAINT ORANGE (-1225 3400);
|
|
DISPLAY INVISIBLE (-1225 3400);
|
|
FORCEPROP 1 LAST PATH I8
|
|
J 0
|
|
(-1575 3575);
|
|
DISPLAY 0.872340 (-1575 3575);
|
|
PAINT PINK (-1575 3575);
|
|
DISPLAY INVISIBLE (-1575 3575);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1550 3525);
|
|
DISPLAY INVISIBLE (-1550 3525);
|
|
FORCEADD INPORT..1
|
|
(-1450 2525);
|
|
FORCEPROP 1 LASTPIN (-1400 2525) VHDL_PORT IN
|
|
J 0
|
|
(-1385 2455);
|
|
DISPLAY 0.872340 (-1385 2455);
|
|
PAINT PINK (-1385 2455);
|
|
DISPLAY INVISIBLE (-1385 2455);
|
|
FORCEPROP 1 LASTPIN (-1400 2525) HDL_PORT IN
|
|
J 0
|
|
(-1125 2400);
|
|
DISPLAY 0.872340 (-1125 2400);
|
|
PAINT ORANGE (-1125 2400);
|
|
DISPLAY INVISIBLE (-1125 2400);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1125 2400);
|
|
DISPLAY 0.872340 (-1125 2400);
|
|
PAINT ORANGE (-1125 2400);
|
|
DISPLAY INVISIBLE (-1125 2400);
|
|
FORCEPROP 1 LAST PATH I9
|
|
J 0
|
|
(-1475 2575);
|
|
DISPLAY 0.872340 (-1475 2575);
|
|
PAINT PINK (-1475 2575);
|
|
DISPLAY INVISIBLE (-1475 2575);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1450 2525);
|
|
DISPLAY INVISIBLE (-1450 2525);
|
|
FORCEADD PENN B SIZE PAGE..1
|
|
(3650 50);
|
|
FORCEPROP 2 LAST CDS_LIB misc
|
|
J 0
|
|
(3650 50);
|
|
DISPLAY INVISIBLE (3650 50);
|
|
FORCEPROP 1 LAST COMMENT_BODY TRUE
|
|
J 0
|
|
(1825 -25);
|
|
DISPLAY 0.872340 (1825 -25);
|
|
PAINT WHITE (1825 -25);
|
|
DISPLAY INVISIBLE (1825 -25);
|
|
WIRE 16 -1 (275 3525)(950 3525);
|
|
FORCEPROP 2 LAST SIG_NAME GT_TTL
|
|
J 0
|
|
(365 3560);
|
|
DISPLAY 1.021277 (365 3560);
|
|
PAINT ORANGE (365 3560);
|
|
WIRE 16 -1 (275 3475)(950 3475);
|
|
FORCEPROP 2 LAST SIG_NAME GT_TTL_OUT
|
|
J 0
|
|
(315 3485);
|
|
DISPLAY 1.021277 (315 3485);
|
|
PAINT ORANGE (315 3485);
|
|
WIRE 16 -1 (275 3425)(950 3425);
|
|
FORCEPROP 2 LAST SIG_NAME GT2_P
|
|
J 0
|
|
(440 3435);
|
|
DISPLAY 1.021277 (440 3435);
|
|
PAINT ORANGE (440 3435);
|
|
WIRE 16 -1 (-1025 3800)(-1500 3800);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC24_P
|
|
J 0
|
|
(-1460 3835);
|
|
DISPLAY 1.021277 (-1460 3835);
|
|
PAINT ORANGE (-1460 3835);
|
|
WIRE 16 -1 (900 4225)(275 4225);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC24_TTL
|
|
J 0
|
|
(365 4235);
|
|
DISPLAY 1.021277 (365 4235);
|
|
PAINT ORANGE (365 4235);
|
|
WIRE 16 -1 (275 4325)(900 4325);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC_TTL
|
|
J 0
|
|
(390 4335);
|
|
DISPLAY 1.021277 (390 4335);
|
|
PAINT ORANGE (390 4335);
|
|
WIRE 16 -1 (275 4025)(925 4025);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC_LVDS_P
|
|
J 0
|
|
(390 4060);
|
|
DISPLAY 1.021277 (390 4060);
|
|
PAINT ORANGE (390 4060);
|
|
WIRE 16 -1 (925 3950)(275 3950);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC_LVDS_N
|
|
J 0
|
|
(390 3960);
|
|
DISPLAY 1.021277 (390 3960);
|
|
PAINT ORANGE (390 3960);
|
|
WIRE 16 -1 (275 3800)(925 3800);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC24_LVDS_P
|
|
J 0
|
|
(365 3860);
|
|
DISPLAY 1.021277 (365 3860);
|
|
PAINT ORANGE (365 3860);
|
|
WIRE 16 -1 (925 3725)(275 3725);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC24_LVDS_N
|
|
J 0
|
|
(365 3760);
|
|
DISPLAY 1.021277 (365 3760);
|
|
PAINT ORANGE (365 3760);
|
|
WIRE 16 -1 (275 3600)(950 3600);
|
|
FORCEPROP 2 LAST SIG_NAME GT_NIM
|
|
J 0
|
|
(390 3635);
|
|
DISPLAY 1.021277 (390 3635);
|
|
PAINT ORANGE (390 3635);
|
|
WIRE 17 -1 (-1400 2525)(-925 2525);
|
|
FORCEPROP 2 LAST SIG_NAME PULSE_IN_ANAL<0..11>
|
|
J 0
|
|
(-1335 2560);
|
|
DISPLAY 1.021277 (-1335 2560);
|
|
PAINT ORANGE (-1335 2560);
|
|
WIRE 16 -1 (-1500 3725)(-1025 3725);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC24_N
|
|
J 0
|
|
(-1460 3735);
|
|
DISPLAY 1.021277 (-1460 3735);
|
|
PAINT ORANGE (-1460 3735);
|
|
WIRE 16 -1 (-1500 3525)(-1025 3525);
|
|
FORCEPROP 2 LAST SIG_NAME GT_N
|
|
J 0
|
|
(-1410 3535);
|
|
DISPLAY 1.021277 (-1410 3535);
|
|
PAINT ORANGE (-1410 3535);
|
|
WIRE 16 -1 (-1500 3600)(-1025 3600);
|
|
FORCEPROP 2 LAST SIG_NAME GT_P
|
|
J 0
|
|
(-1435 3635);
|
|
DISPLAY 1.021277 (-1435 3635);
|
|
PAINT ORANGE (-1435 3635);
|
|
WIRE 16 -1 (-1500 3925)(-1025 3925);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC_N
|
|
J 0
|
|
(-1435 3935);
|
|
DISPLAY 1.021277 (-1435 3935);
|
|
PAINT ORANGE (-1435 3935);
|
|
WIRE 16 -1 (-1025 4000)(-1500 4000);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC_P
|
|
J 0
|
|
(-1435 4035);
|
|
DISPLAY 1.021277 (-1435 4035);
|
|
PAINT ORANGE (-1435 4035);
|
|
WIRE 16 -1 (950 3350)(275 3350);
|
|
FORCEPROP 2 LAST SIG_NAME GT2_N
|
|
J 0
|
|
(440 3385);
|
|
DISPLAY 1.021277 (440 3385);
|
|
PAINT ORANGE (440 3385);
|
|
WIRE 17 -1 (150 2300)(775 2300);
|
|
FORCEPROP 2 LAST SIG_NAME SCOPE_OUT_ANAL<0..7>
|
|
J 0
|
|
(215 2310);
|
|
DISPLAY 1.021277 (215 2310);
|
|
PAINT ORANGE (215 2310);
|
|
WIRE 17 -1 (150 2425)(775 2425);
|
|
FORCEPROP 2 LAST SIG_NAME CAEN_OUT_ANAL<0..7>
|
|
J 0
|
|
(240 2460);
|
|
DISPLAY 1.021277 (240 2460);
|
|
PAINT ORANGE (240 2460);
|
|
WIRE 16 -1 (-925 1925)(-1400 1925);
|
|
FORCEPROP 2 LAST SIG_NAME DATA_RDY
|
|
J 0
|
|
(-1360 1960);
|
|
DISPLAY 1.021277 (-1360 1960);
|
|
PAINT ORANGE (-1360 1960);
|
|
WIRE 16 -1 (-1400 2000)(-925 2000);
|
|
FORCEPROP 2 LAST SIG_NAME LE
|
|
J 0
|
|
(-1310 2010);
|
|
DISPLAY 1.021277 (-1310 2010);
|
|
PAINT ORANGE (-1310 2010);
|
|
WIRE 16 -1 (-1400 2100)(-925 2100);
|
|
FORCEPROP 2 LAST SIG_NAME CLK
|
|
J 0
|
|
(-1310 2135);
|
|
DISPLAY 1.021277 (-1310 2135);
|
|
PAINT ORANGE (-1310 2135);
|
|
WIRE 16 -1 (-925 2175)(-1400 2175);
|
|
FORCEPROP 2 LAST SIG_NAME DATA
|
|
J 0
|
|
(-1335 2235);
|
|
DISPLAY 1.021277 (-1335 2235);
|
|
PAINT ORANGE (-1335 2235);
|
|
FORCENOTE
|
|
11
|
|
(3125 100) 0;
|
|
DISPLAY LEFT (3125 100);
|
|
DISPLAY 1.021277 (3125 100);
|
|
PAINT PURPLE (3125 100);
|
|
FORCENOTE
|
|
CAEN COMMS
|
|
(-3350 4700) 0;
|
|
DISPLAY LEFT (-3350 4700);
|
|
DISPLAY 3.148936 (-3350 4700);
|
|
PAINT PURPLE (-3350 4700);
|
|
FORCENOTE
|
|
11D
|
|
(-525 4100) 0;
|
|
DISPLAY LEFT (-525 4100);
|
|
DISPLAY 1.021277 (-525 4100);
|
|
PAINT PURPLE (-525 4100);
|
|
FORCENOTE
|
|
11A
|
|
(-500 2200) 0;
|
|
DISPLAY LEFT (-500 2200);
|
|
DISPLAY 1.021277 (-500 2200);
|
|
PAINT PURPLE (-500 2200);
|
|
QUIT
|