32 lines
670 B
Verilog
32 lines
670 B
Verilog
// generated by newgenasym Mon May 18 15:57:16 2015
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module caen_dig_coms (gt2_n, gt2_p, gt_n, gt_nim, gt_p, gt_ttl, gt_ttl_out,
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sync24_lvds_n, sync24_lvds_p, sync24_n, sync24_p,
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sync24_ttl, sync_lvds_n, sync_lvds_p, sync_n, sync_p,
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sync_ttl);
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output gt2_n;
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output gt2_p;
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input gt_n;
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output gt_nim;
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input gt_p;
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output gt_ttl;
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output gt_ttl_out;
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output sync24_lvds_n;
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output sync24_lvds_p;
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input sync24_n;
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input sync24_p;
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output sync24_ttl;
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output sync_lvds_n;
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output sync_lvds_p;
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input sync_n;
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input sync_p;
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output sync_ttl;
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initial
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begin
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end
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endmodule
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