Tubii_Tk2/worklib/caen_ports/entity/verilog.v
2015-03-06 19:02:51 -05:00

21 lines
454 B
Verilog

// generated by newgenasym Fri Mar 06 18:55:27 2015
module caen_ports (caen_out_anal, gt_nim, pulse_in_anal, scope_out_anal,
sync24_lvds_n, sync24_lvds_p, sync_lvds_n, sync_lvds_p);
input [0:7] caen_out_anal;
input gt_nim;
output [0:11] pulse_in_anal;
input [0:7] scope_out_anal;
input sync24_lvds_n;
input sync24_lvds_p;
input sync_lvds_n;
input sync_lvds_p;
initial
begin
end
endmodule