17 lines
513 B
VHDL
17 lines
513 B
VHDL
-- generated by newgenasym Fri Mar 06 18:55:27 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity caen_ports is
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port (
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CAEN_OUT_ANAL: IN STD_LOGIC_VECTOR (0 TO 7);
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GT_NIM: IN STD_LOGIC;
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PULSE_IN_ANAL: OUT STD_LOGIC_VECTOR (0 TO 11);
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SCOPE_OUT_ANAL: IN STD_LOGIC_VECTOR (0 TO 7);
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SYNC24_LVDS_N: IN STD_LOGIC;
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SYNC24_LVDS_P: IN STD_LOGIC;
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SYNC_LVDS_N: IN STD_LOGIC;
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SYNC_LVDS_P: IN STD_LOGIC);
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end caen_ports;
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