26 lines
577 B
Verilog
26 lines
577 B
Verilog
// generated by newgenasym Tue Mar 03 16:31:26 2015
|
|
|
|
|
|
module change_clks (bckp_clk2_n, bckp_clk2_p, bckp_clk3_n, bckp_clk3_p,
|
|
bckp_used, change_clk_n, change_clk_p, clk100_n, clk100_p,
|
|
clk100_ttl, default_clk2_n, default_clk2_p);
|
|
input bckp_clk2_n;
|
|
input bckp_clk2_p;
|
|
input bckp_clk3_n;
|
|
input bckp_clk3_p;
|
|
output bckp_used;
|
|
input change_clk_n;
|
|
input change_clk_p;
|
|
output clk100_n;
|
|
output clk100_p;
|
|
output clk100_ttl;
|
|
input default_clk2_n;
|
|
input default_clk2_p;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|