15 lines
222 B
Verilog
15 lines
222 B
Verilog
// generated by newgenasym Fri Mar 06 17:55:51 2015
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module clock_ports (clk100_n, clk100_p, tub_clk_in);
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input clk100_n;
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input clk100_p;
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output tub_clk_in;
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initial
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begin
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end
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endmodule
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