12 lines
272 B
VHDL
12 lines
272 B
VHDL
-- generated by newgenasym Fri Mar 06 17:55:51 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity clock_ports is
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port (
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CLK100_N: IN STD_LOGIC;
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CLK100_P: IN STD_LOGIC;
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TUB_CLK_IN: OUT STD_LOGIC);
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end clock_ports;
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