Tubii_Tk2/worklib/ecal_control/entity/verilog.v
2015-02-28 19:01:09 -05:00

16 lines
253 B
Verilog

// generated by newgenasym Sat Feb 28 19:00:43 2015
module ecal_control (ecal_active, ext_ped_in, ext_ped_out, gt);
input ecal_active;
input ext_ped_in;
output ext_ped_out;
input gt;
initial
begin
end
endmodule