13 lines
312 B
VHDL
13 lines
312 B
VHDL
-- generated by newgenasym Sat Feb 28 19:00:43 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ecal_control is
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port (
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ECAL_ACTIVE: IN STD_LOGIC;
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EXT_PED_IN: IN STD_LOGIC;
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EXT_PED_OUT: OUT STD_LOGIC;
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GT: IN STD_LOGIC);
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end ecal_control;
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