30 lines
772 B
Verilog
30 lines
772 B
Verilog
// generated by newgenasym Thu Mar 05 12:44:02 2015
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module ecl_translation (ecl_to_lvds_in, ecl_to_lvds_out_n, ecl_to_lvds_out_p,
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ecl_to_nim_in, ecl_to_nim_out, ecl_to_ttl_in,
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ecl_to_ttl_out, lvds_to_ecl_in_n, lvds_to_ecl_in_p,
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lvds_to_ecl_out, nim_to_ecl_in, nim_to_ecl_out,
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ttl_to_ecl_in, ttl_to_ecl_out);
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input ecl_to_lvds_in;
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output ecl_to_lvds_out_n;
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output ecl_to_lvds_out_p;
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input ecl_to_nim_in;
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output ecl_to_nim_out;
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input ecl_to_ttl_in;
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output ecl_to_ttl_out;
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input lvds_to_ecl_in_n;
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input lvds_to_ecl_in_p;
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output lvds_to_ecl_out;
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input nim_to_ecl_in;
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output nim_to_ecl_out;
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input ttl_to_ecl_in;
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output ttl_to_ecl_out;
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initial
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begin
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end
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endmodule
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