28 lines
760 B
Verilog
28 lines
760 B
Verilog
// generated by newgenasym Thu Mar 05 19:38:55 2015
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module ellie_coms (smellie_delay_out, smellie_delay_out_ttl,
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smellie_pre_delay_ecl, smellie_pre_delay_ttl,
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smellie_pulse, smellie_pulse_out, tellie_delay_out,
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tellie_delay_out_ttl, tellie_pre_delay_ecl,
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tellie_pre_delay_ttl, tellie_pulse, tellie_pulse_out);
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output smellie_delay_out;
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input smellie_delay_out_ttl;
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input smellie_pre_delay_ecl;
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output smellie_pre_delay_ttl;
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input smellie_pulse;
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output smellie_pulse_out;
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output tellie_delay_out;
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input tellie_delay_out_ttl;
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input tellie_pre_delay_ecl;
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output tellie_pre_delay_ttl;
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input tellie_pulse;
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output tellie_pulse_out;
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initial
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begin
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end
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endmodule
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