14 lines
219 B
Verilog
14 lines
219 B
Verilog
// generated by newgenasym Thu Apr 23 11:02:22 2015
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module ellie_ports (smellie_delay_in, tellie_delay_in);
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output smellie_delay_in;
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output tellie_delay_in;
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initial
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begin
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end
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endmodule
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